In this specification, the term integrated circuit is used to indicate a single chip or MCM (multi-chip module), while the term circuit assembly is used to indicate a combination of integrated circuits.
An integrated circuit or circuit assembly generally contains multiple clocks, either generated internally or controlled externally. Each clock is distributed to a set of storage cells via a skew-minimized network, which delivers a clock pulse to all the storage cells at virtually the same time. Such a clock, its related storage cells, and all combinational logic blocks bounded by the storage cells, form a clock domain. It should be noted that, however, although the clock skew of any clock domain is minimized, the clock skew between any two clock domains could be large and unpredictable.
Scan design is the most widely used design-for-test technique, which replaces all or part of original storage cells with scan cells that form one or more scan chains. A scan-based integrated circuit or circuit assembly can be tested by repeating a shift cycle followed by a capture cycle. In a shift cycle, pseudorandom or predetermined test stimuli are shifted into all scan cells, making their outputs as controllable as primary inputs. In a capture cycle, test responses are latched into some or all scan cells, making their inputs as observable as primary outputs, because the values captured into scan cells can be shifted out in the next shift cycle.
Now consider the testing of a scan-based integrated circuit or circuit assembly with multiple clock domains. In a shift cycle, since scan cells in different clock domains are usually connected into different scan chains, it is easy to guarantee that each scan chain operates correctly as a shift register. In a capture cycle, however, a race problem might occur due to multiple clock domains. For example, suppose that clock domain CD1 is connected to clock domain CD2 through a crossing clock-domain logic block. In this case, if both clock domains capture at the same time, clock domain CD2 may capture different values depending on the clock skew between the two clock domains CD1 and CD2. This race problem in a capture cycle makes it difficult to test a scan-based integrated circuit or circuit assembly with multiple clock domains, in either scan-test or self-test mode.
Prior-art solutions for this race problem are based on either a single-capture approach or a multiple-capture approach, depending on if skewed capture clock pulses are applied to multiple clock domains in one capture cycle. The prior-art solutions based on the single-capture approach include the isolated DFT (design-for-test) technique (prior-art solution #1), the ratio'ed DFT technique (prior-art solution #2), and the one-hot DFT technique (prior-art solution #3), while the prior-art solutions based on the multiple-capture approach include four solutions, two for scan-test (prior-art solution #4 and prior-art solution #5), one for self-test (prior-art solution #6), and one for both scan-test and self-test (prior-art solution #7), as summarized bellow:
Prior-art solution #1 is described in U.S. Pat. No. 6,327,684 by Nadeau-Dostie et al. (2001). In this so-called isolated DFT technique, signal propagation from one clock domain to another is blocked by adding additional logic, thus preventing any adverse effect caused by the potential race problem. This solution, however, suffers from several disadvantages: First, it requires that blocking logic be inserted between interacting clock domains, which has adverse impact on design cost, chip size, and performance. Second, the scan enable signal associated with each clock domain should be able to operate at-speed, which requires complicated routing as in CTS (clock tree synthesis). Third, since two clock domains may interact with each other in both directions, crossing clock-domain faults have to be tested in two or more test sessions. This bi-directional interaction not only increases the test time but also complicates blocking logic insertion.
Prior-art solution #2 is described in U.S. Pat. No. 5,349,587 by Nadeau-Dostie et al. (1994). In this so-called ratio'ed DFT technique, the clocks for all clock domains are required to operate at one of three frequencies: F, F/2, and F/4, where F is the highest system clock frequency or a reference clock frequency. For example, even though a design has 3 clocks running at 150 MHz, 80 MHz, and 45 MHz, respectively, they have to be reconfigured to operate at 150 MHz, 75 MHz, and 37.5 MHz, respectively, during test. This technique makes it easy to align capture clock pulses for all clock domains which is capable of testing all clock domains and all crossing clock-domain logic blocks in parallel. This solution, however, suffers from several disadvantages: First, the test quality of this technique is low since test clock frequencies are not at-speed for all clock domains. Second, this technique requires a clock pre-scaler which increases the risk of clock glitches. Third, this technique requires significant physical design efforts related to aligning capture clock edges for all clock domains. Finally, power consumption could be too high since all scan cells are triggered simultaneously every few clock cycles.
Prior-art solution #3 is described in U.S. Pat. No. 5,680,543 by Bhawmik et al. (1997). The first step in this so-called one-hot DFT technique is to initialize all crossing clock-domain signals flowing into their receiving clock domains by shifting in predetermined logic values to all clock domains. The second step is to test one clock domain after another. The major advantage of this technique is its ability to detect or locate crossing clock-domain faults without inserting any blocking logic into any paths, in particular critical paths. This solution, however, suffers from several disadvantages: First, this technique tests one clock domain at a time, resulting in long test time. Second, it requires significant design and layout efforts for synchronizing all clock domains.
Prior-art solution #4 and prior-art solution #5 are described in U.S. Pat. No. 6,070,260 by Buch et al. (2000) and U.S. Pat. No. 6,195,776 by Ruiz et al. (2001), respectively. These multiple-capture DFT techniques are proposed to test faults within each clock domain and faults between any two clock domains in scan-test mode. These techniques use multiple skewed scan clocks or multiple skewed capture events, each operating at the same reduced clock speed, in an ATE (automatic test equipment), to detect or locate faults. Combinational ATPG (automatic test pattern generation) is used to generate scan patterns, and ATE test programs are created, to detect or locate faults in an integrated circuit or circuit assembly. These solutions, however, suffer from a major disadvantage that they apply only one capture clock pulse to each clock domain in a capture cycle. This means that only stuck-at faults can be detected or located in scan-test mode. Delay faults, as well as stuck-at faults in a partial scan design, cannot be detected or located since multiple skewed capture clock pulses are needed for that purpose.
Prior-art solution #6 is described in a paper by Hetherington et al. (1999). This multiple-capture DFT approach is proposed to test faults within each clock domain and faults between any two clock domains in self-test mode. This technique basically generates a transition during the last shift-in operation, and then capture the test response to the transition with an at-speed capture clock pulse. This at-speed capture is conducted in a programmable capture window on all clock domains to detect or locate faults within each clock domain and faults between any two clock domains. This solution, however, suffers from two disadvantages: First, this technique requires complicated clock manipulation including clock suppression and clock multiplexing, which increases the risk of clock glitches. Second, the last shift clock edges need to be precisely aligned for all clock domains, which makes it difficult to perform at-speed self-test for integrated circuits with clock domains operating at unrelated frequencies, e.g. 60 MHz and 133 MHz.
Prior-art solution #7 is described in International Patent Application No. PCT/US 02/01251 by Wang et al. (2002). This multiple-capture DFT technique applies a sequence of ordered capture clocks to all clock domains in a capture cycle. This technique can be used to test faults within each clock domain and faults between any two clock domains in either self-test or scan-test mode. Both stuck-type faults, including open, IDDQ (IDD quiescent current), and bridging faults, as well as delay-type faults, including transition or gate-delay, path-delay, and multiple-cycle delay faults, can be detected or located. In addition, both reduced-speed (slow-speed) test and at-speed test can be conducted. The key advantage of the technique is that no clock edge alignment in either a shift cycle or a capture cycle is needed, making it easy to complete physical design. Another key feature of the technique is the use of two capture clock pulses in testing delay-type faults, which requires processing more time frames in fault simulation or ATPG (automatic test pattern generation). For a very large scale integrated circuit, efforts should be made to reduce time needed for such fault simulation or ATPG.
Therefore, there is a need for an improved scan design system, comprising a method, apparatus, and a CAD (computer-aided design) system, which uses a multiple-capture DFT technique to conduct at-speed or slow-speed testing of both stuck-type and delay-type faults within each clock domain and between any two clock domains in an integrated circuit or circuit assembly. This multiple-capture DFT technique should be less intrusive (refer to prior-art solution #1), changes no clock frequencies during test (refer to prior-art solution #2), applies capture clock pulses to all clock domains in each capture cycle (refer to prior-art solution #3), can apply multiple capture clock pulses for one clock domain to detect or locate delay-type faults (refer to prior-art solution #4 and prior-art solution #5), needs less clock manipulation (refer to prior-art solution #6), and processes less time frames in fault simulation or ATPG (automatic test pattern generation) (refer to prior-art solution #7).
In addition to the race problem discussed above, the testing of a scan-based integrated circuit or circuit assembly with multiple clock domains also suffers from some problems related to fault simulation in both self-test and scan-test modes and ATPG in scan-test mode. Prior-art solutions for fault simulation or ATPG related problems are based on either a single-capture approach or a multiple-capture approach, depending on if skewed clock pulses are applied to multiple clock domains in one capture cycle. The prior-art solution based on the single-capture approach includes the one-hot DFT technique (prior-art solution #8), while the prior-art solution based on the multiple-capture approach includes the PCE (primary capture event) based ATPG technique (prior-art solution #9), as summarized below:
Prior-art solution #8 is known as the so-called one-hot DFT technique. The major disadvantage of this technique is that the number of test patterns tends to be large since the capture clock is active for only one clock domain in each capture cycle. This results in not only long test time but also large test data volume, which will in turn increase the test cost.
Prior-art solution #9 is described in U.S. Pat. No. 6,195,776 by Ruiz et al. (2001). The DFT (design-for-test) technique uses multiple skewed capture events for all clock domains in one capture cycle to test faults in an integrated circuit, which is composed of a combinational logic portion and scan cells. When this DFT technique is applied, the circuit behavior during a capture cycle can be fully represented by several copies of the combinational logic portion, each with a different set of constraints on its inputs and outputs and each corresponding to a time frame. In the fault simulation or ATPG solution associated with this DFT technique, only one copy of the combinational logic portion corresponding to the so-called PCE (primary capture event) is selected for circuit transformation. As a result, a combinational circuit model is obtained to perform fault simulation or ATPG. The disadvantage of this solution is that all other copies of the combinational logic portion are discarded, and that some of the constrained values on the selected copy are set to unknown values. Obviously, the fault coverage will be low given a certain number of test patterns. To increase the fault coverage, a large number of test patterns may have to be used. In addition, this DFT technique forces unknown values on asynchronous set/reset pins to avoid any destructive race problem. However, this will result in lower fault coverage due to the unknown values.
Therefore, there is also a need for an improved fault simulation or test pattern generation system, comprising a method and a CAD system, that uses a fault simulation or ATPG solution to achieve a high coverage with a small number of test patterns for both stuck-type and delay-type faults within each clock domain and between any two clock domains in an integrated circuit or circuit assembly implemented with a multiple-capture DFT technique. The memory size needed to implement the fault simulation or ATPG solution should be as small as possible. In addition, the ATPG solution should be able to properly handle such special structures as asynchronous set/reset pins, tri-state buses, and low-power gated clocks. Furthermore, there is a need for an improved apparatus that can properly handle such special structures as asynchronous set/reset signals, tri-state busses, and low-power gated clocks.